80196 In Circuit Emulators
key features
user interface
complex events
trace buffer

80196 emulator brochure data sheet

80196 emulator

80196 in circuit emulator, 80196 emulator, 80196 emulators, 80196 ICE, 80196 software, 80196 debugger, 80196 hardware, 80196 development tools, 80196 embedded systems.

KEY FEATURES 80196 emulator features

Memory display and edit while executing (USP-96)
Trace view during execution
Interrupts executed during breakpoints (Background Monitor option)
HLL source debugger for C-96 and PL/M-96
Pass-points to monitor internal RAM variables and registers while executin
Real-time transparent emulation up to 20 MHz
Up to 32K of execution Trace Buffer with filtering
32-bit real-time stamp in trace
Up to 256K of overlay Program RAM with bank switching
Unlimited number of hardware breakpoints
Three complex events for breakpoints and trace filtering
Two 16 bit Pass Counters with Stop/Reload
8-level hardware event sequencer
8-channel user logic state analyzer
External trigger input and outputs
Wide range of ÁP pods to emulate most MCS-96 family members
Remote debugging over TCP/IP network
Win95 and NT user interface
Serial interface to the host PC

USER INTERFACE 80196 emulator GUI

The Win95 and NT user interface is designed to work with the Pentium computers and provides multiple windows for Source, Registers, Memory, Stack, Variables, Locals, Commands, Coverage Analysis, and others. The source level debugger window is capable of working with all major C-96 and PL/M-96 compilers and links symbols automatically to the Trace window. The user defined SFR and variable Watch windows complement the suite. Extensive Macro support allows you to add even more power to this rich and yet intuitive man-machine interface.

COMPLEX EVENTS 80196 emulator complex events

Complex Event is a set of conditions that qualify 80196 emulation Breakpoints, Event Sequencer, or trace filtering in real-time. There are 5 complex events that may be qualifie th:
64K/256K address match space
8/16-bit Data match
RD, WR, INT, instruction fetch
External input with programmable trigger polarity

All events may be counted or delayed by the use of two 16 bit Pass Counters. An eight level hardware sequencer is available to sequentially trigger from any 80196 emulator Event or Pass Counter.

BREAKPOINTS 80196 emulator breakpoints

Breakpoints are used to stop user program execution while preserving the current program status. They may be triggered from a combination of:

Address or Range of Addresses
Complex Events 
External Input 
Pass Counters 
Trace Buffer Full Condition

TRACE BUFFER 80196 emulator trace

Trace buffer is a high speed RAM used to capture in real time all activity on the microprocessor internal bus and pins. A dedicated start/stop logic allows for filtering unwanted information from the trace buffer while executing. Trace will store up to 32 K samples comprised of the following:
Address Bus
Data Bus
Control signals
I/O pins
Real Time Clock Stamp
8-ch. user logic state analyzer

The trace can be collected selectively with the use of complex events. After capture it may be post-filtered using a variety of options from the trace filtering menu. The trace is equipped with an internal counter to allow tracing to stop after a specified number of frames have been captured. This feature allows the trace to capture as much as 32K of small program fragments no matter how distant in time, using only one event. The trace contents may be viewed during program execution without stopping or slowing down the microcontroller.

SPECIFICATIONS 80196 emulator specifications

model: USP-196       

Supported Microcontrollers
8095BH, 8096BH, 8097BH
8xC196KB, 8xC196KB-16, 8xC198, 8xC194
8xC196KC, 8xC196KC-20
8xC196KD, 8xC196KD-20
8xC196KR, 8xC196JR, 8xC196KQ, 8xC196JQ, 8xC196KT
Maximum emulation speed
20 MHz
260 mm wide, 260 mm deep, 64 mm high
Maximum Emulation Program Memory
Program Memory Mapping
256 byte boundary
Data Memory Mapping
256 byte boundary
Pass Counters
two, 16-bit each
Trace buffer
32K * 80 bits, pre- and post-filtering
Real_Time Stamp
32-bits, 100 ns resolution
hardware, 8 levels
User probe
8 channel logic input
1 trigger input with gate
6 trigger outputs (Events, Pass Counters, Sequencer)
Host interface
RS-232C, 9600-115 KBaud, XON/XOFF
File upload/download format
Intel HEX/AOMF, IAR, and Tasking

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